This invention relates to systems and methods for reading information stored on a magnetic medium.
In a magnetic disk storage system, a read channel extracts information stored on a magnetic disk and delivers that information to a host system (e.g., a computer). The magnetic disk is formatted with a plurality of concentric data tracks, each of which is configured to store a fixed quantity of data in the form of magnetic transitions on the disk surface. A spindle motor rotates the magnetic disk and a magnetic transducer positioned adjacent to the disk senses the magnetic transitions on the disk surface and produces an input read signal corresponding to the recorded data. The read channel includes a plurality of components for reconstructing the recorded data from the input read signal received from the transducer. Sampled amplitude read channels include components (e.g., a digital wave shaping circuit and a digital filter) for equalizing the input read signal into a predetermined partial response (e.g., PR4 or EPR4) that enables the output of the read channel to be approximated as a linear combination of time delayed pulses modulated by a binary sequence.
Before a sampled amplitude read channel can detect and decode the data symbols encoded in the data signal being read from a magnetic disk, the data samples must be synchronized to the baud rate (i.e., the rate at which data was written to the magnetic medium). Some read channels include a single sampling timing recovery loop that synchronizes a sampling clock to the baud rate by minimizing an error between the data samples and estimated sample values. Other read channels (e.g., the sampled amplitude read channel described in U.S. Pat. No. 5,696,639) include a single interpolating timing recovery loop that synchronizes asynchronously sampled data values to produce interpolated sample values that are approximately synchronized to the baud rate.
The invention features a system and a method for reading information stored on a magnetic medium by generating data symbols from a signal encoded at a baud rate with data including an acquisition preamble defining an acquisition frequency and an acquisition phase. The system includes an inventive dual loop synchronizer that is optimized to improve the operating efficiency and reduce the overall latency of the read channel.
In one aspect of the invention, the dual loop synchronizer includes a frequency synchronization loop, a signal sampler, an interpolator, and a phase synchronization loop. The frequency synchronization loop is configured to generate a sampling clock synchronized approximately to the acquisition frequency and the acquisition phase of the encoded data signal. The signal sampler is coupled to the frequency synchronization loop and is configured to sample the encoded data signal in response to the sampling clock to produce a plurality of data samples. The interpolator is coupled to the frequency synchronization loop and is configured to produce in response to the sampling clock interpolated samples from the data samples. The phase synchronization loop is coupled to the interpolator and is configured to synchronize the interpolator to the baud rate of the encoded data signal.
In another aspect of the invention, the frequency synchronization loop comprises a delay-locked loop configured to synthesize the sampling clock.
Embodiments may include one or more of the following features.
The delay-locked loop preferably comprises a phase detector and a filter coupled in series and configured to control signal propagation delay through the delay-locked loop. A fixed frequency signal generator preferably is coupled to the delay-locked loop. A feedback loop may be coupled between an output of the signal sampler and an input of the frequency synchronization loop. The feedback loop preferably comprises a phase detector configured to generate a phase error signal based upon the difference between estimated samples and the data samples. The feedback loop preferably also comprises a loop filter configured to filter the phase error signal to produce a filtered phase error signal operable to synchronize the synthesized sampling clock approximately to the acquisition frequency of the encoded data signal.
The phase synchronization loop may comprise a phase detector configured to generate a phase error signal based upon the difference between estimated samples and the data samples. The phase synchronization loop may be configured to time-shift the response of the interpolator. The phase synchronization loop preferably comprises a memory storing a plurality of sets of coefficients, wherein each coefficient set defines an interpolator response shifted in time relative to the other coefficient sets. The phase synchronization loop may be configured to time-shift the interpolator response by only a fraction of a sampling clock period. A phase calibrator may be coupled between the frequency synchronization loop and the phase synchronization loop and may be configured to calibrate the frequency synchronization loop after an accumulation of phase errors generated by the phase detector of the phase synchronization loop exceeds a threshold value. The phase calibrator may be configured to calibrate the frequency synchronization loop by adjusting the sampling clock phase or the sampling clock frequency, or both. The phase calibrator preferably comprises a feedback isolator for approximately canceling a phase transient generated at the phase synchronization loop as a result of a frequency synchronization loop calibration.
The frequency synchronization loop may be configured to fix the sampling clock frequency before the signal sampler has sampled the entire acquisition preamble of the encoded data signal. The phase synchronization loop may be configured to synchronize the interpolator during and after the signal sampler has sampled the entire acquisition preamble of the encoded data signal.
Among the advantages of the invention are the following.
By synchronizing the data samples to the baud rate with two separate control loops, each of which is optimized for operation during particular periods of each read cycle, the overall read channel latency (e.g., the latency generated by any analog-to-digital converters and any finite impulse response filters) may be significantly reduced. Furthermore, the invention improves the synchronization accuracy of the read channel while reducing the complexity of the components needed to synchronize the data samples to the baud rate. Also, because the frequency synchronization loop approximately synchronizes the data samples to the baud rate, the phase synchronization loop need only cover a limited interpolation window (e.g., xc2x125% of a bit period, or less). This allows the design of the associated interpolation filter, which equalizes the data samples to a predetermined spectrum, to be significantly simplified.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.